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Folded Source-Coupled Logic (FSCL) Although the CML logic gate is biased using a constant current source, a large displacement pulse can still flow in the power supply lines during state transitions, if significant load capacitance is connected in parallel with the current source. To further reduce the undesired current pulses and signal swings, a folded sourcecoupled logic (FSCL) has been proposed.10 This logic family is a modified version of the source coupled logic (SCL) logic. The operating principal, like SCL, is also based on current steering. As shown in Figure 9.9, it comprises a NMOS sourcecoupled pair biased with constant caITent I, and diode-connected (drain-gate shorted) output stages, each biased with a constant current 12 provided by PMOS current source (Q5 and Q6). With a positi ve full-differential input voltage applied to the FSCL inverter, 11 flows through Q1 and zero flows through Q2, therefore 13 = 12 - I1 and 14 = 12. The diode-connected load device converts 13 and 14 to fulldifferential output voltages: how to make barcodes in excel 2003 Using the Barcode Font in Microsoft Excel (Spreadsheet)
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